1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to a nonvolatile semiconductor memory and a method of manufacturing the same.
A flash memory, which is a nonvolatile semiconductor memory having a simple device structure suitable for high integration like a DRAM, is used in a wide variety of information processing apparatuses including computers and mobile phones. Generally, in the flash memory, information is retained in the form of an electric charge using a floating gate.
On the other hand, recently, there has been proposed a nonvolatile semiconductor memory having an MONOS (metal-oxide-nitride-oxide-semiconductor) or SONOS (semiconductor-oxide-nitride-oxide-semiconductor) structure using an insulating film having an ONO structure as the gate insulating film of a MOS transistor so that the nonvolatile semiconductor memory retains information in the form of an electric charge in the ONO gate insulating film. In the nonvolatile semiconductor memory having the MONOS or SONOS structure, multi-level information may be retained by injecting an electric charge into the gate insulating film from the source or drain side.
2. Description of the Related Art
FIG. 1 is a diagram showing the circuit configuration of a conventional NOR/AND-type nonvolatile semiconductor memory 10 having a SONOS structure.
Referring to FIG. 1, the nonvolatile semiconductor memory 10 includes a memory cell array M in which a plurality of memory cell transistors M11 through Mmm each having a gate insulating film of an ONO structure are arranged in a matrix-like manner. In the memory cell array M, a group of memory cell transistors arranged in a row are connected to any of word lines WLn, WLn+1, WLn+2, WLn+3, . . . in their gate electrodes. Further, a group of memory cell transistors arranged in a column are connected to any of data bit lines DBLh, DBLh+1, DBLh+2, DBLh+3, DBLh+4, . . . in their source diffusion regions and their drain diffusion regions.
Further, the nonvolatile semiconductor memory 10 includes selection gate lines SG1, SG2, SG3, SG4, . . . . The data bit lines DBLh and DBLh+2 are connected to the corresponding main bit line MBLh via selection transistors T1 and T2 connected to the selection gate lines SG1 and SG2. The data bit lines DBLh+1 and DBLh+3 are connected to the corresponding main bit line MBLh+1 via selection transistors T3 and T4 connected to the selection gate lines SG3 and SG3.
In this configuration, information is injected, in the form of channel hot electrons, into the gate insulating films of the ONO structure of the memory cell transistors M11, M12, . . . from their source or drain regions, and is retained.
FIG. 2 is a diagram showing the configuration of a transistor 20 forming each of the memory cell transistors M11, M12, . . . in the memory cell array M.
Referring to FIG. 2, the transistor 20 is formed on a Si substrate 21. Buried diffusion regions 21A and 21B are formed in the Si substrate 21 as source and drain regions, respectively. Further, the surface of the substrate 21 is covered with an ONO film 22 of layers of an oxide film 22a, a nitride film 22b, and an oxide film 22c. A polysilicon gate electrode 23 is formed on the ONO film 22.
FIGS. 3A and 3B are diagrams showing a writing operation and an erasing operation, respectively, in the memory cell transistor of FIG. 2.
Referring to FIG. 3A, at the time of writing information, the source region 21A is grounded while a large positive voltage +VW is applied to the drain region 21B and a large positive voltage +VG1 is applied to the gate electrode 23. As a result, electrons are accelerated on the drain end in the channel region so that hot electrons are generated in the channel. The hot electrons thus formed are injected into the ONO film 22. The injected hot electrons are retained in the ONO film 22 in a part close to the above-described drain end (hereinafter, this part is referred to as a drain-end region). By performing switching so that the driving voltage is applied to the source region 21A instead of the drain region 21B, hot electrons may also be injected in the ONO film 22 in a part close to the source end of the channel region (hereinafter, this part is referred to as a source-end region). As a result, in the memory cell transistor 20 of FIG. 2, it is possible to perform writing of two bits per cell shown in FIG. 1.
Meanwhile, at the time of erasing written information, a large positive voltage +Ve is applied to the drain region 21B and a large negative voltage −VG2 is applied to the gate electrode 23 as shown in FIG. 3B. Thereby, holes are injected into the ONO film 22 from the drain region 21B, so that the electrons stored in the drain-end region of the ONO film 22 disappear. When the electrons are stored in the source-end region of the ONO film 22, the injection of holes may be performed from the source region 21A.
Further, in the case of reading out information written in the drain-end region of the ONO film 22, a predetermined gate voltage Vg is applied to the gate electrode 23 while the drain region 21B is grounded and a reading voltage Vr is applied to the source region 21A as shown in FIGS. 4A and 4B. As a result, if no electrons are stored in the drain-end region of the ONO film 22, carriers are allowed to flow from the drain region 21B through the channel formed right below the gate electrode 23 to the source region 21A in the Si substrate 21, so that the memory cell transistor 20 conducts electricity. On the other hand, if electrons are stored in the drain-end region of the ONO film 22, the channel right below the gate electrode 23 is blocked at the drain end so that the memory cell transistor 20 conducts no electricity.
In the case of reading out information written to the source-end region of the ONO film 22, the source region 21A may be grounded and the reading voltage Vr may be applied to the drain region 21B in FIGS. 4A and 4B.
FIG. 5 is a plan view of a memory integrated circuit including such a SONOS-type flash memory, showing the configuration of the memory cell array of the memory integrated circuit. FIG. 6A is a sectional view of the memory cell array of FIG. 5 taken along the line 1-1′. FIG. 6B is a sectional view of the isolation structure and its periphery of a peripheral circuit not shown in FIG. 5.
Referring first to the sectional view of FIG. 6A, n-type regions 41A forming a bit-line diffusion layer are formed on a p-type Si substrate 41 parallel to each other. Each of the n-type regions 41A is surrounded by a p-type punch-through preventing diffusion layer 41a. 
An insulating film 42 having a so-called ONO structure of layers of a SiO2 film, a SiN film, and a SiO2 film is deposited on the surface of the Si substrate 41. Word line patterns 43 each formed of layers of a polysilicon film 43A and a WSi film 43B are formed on the ONO film 42 parallel to each other so as to cross the drain or source regions 41A at right angles as shown in FIG. 5. As a result, the SONOS-type flash memory cells previously described with reference to FIG. 2 are formed along the cross section of FIG. 6A.
Further, as shown in the plan view of FIG. 5, a p-type isolation diffusion layer 41B is formed in the region of the surface of the Si substrate 41 excluding the regions right below the word lines 43 and the bit-line diffusion layer 41A including the punch-through preventing diffusion layer 41a. The isolation diffusion layer 41B is not shown in the sectional view of FIG. 6A.
Further, as shown in the plan view of FIG. 5, the word lines 43 are connected to word line interconnect patterns WLn+1, WLn+2, WLn+3, . . . WLn+i at contact holes 43C. The bit-line diffusion regions 41A are connected to bit line interconnect patterns BLn+1, BLn+2, BLn+3, . . . BLn+i at contact holes 41C.
On the other hand, as shown in FIG. 6B, a peripheral circuit that cooperates with the memory cells of FIG. 5 and FIG. 6A has an isolation structure 41S of an STI (shallow trench isolation) type. A gate oxide film 52 is formed on the surface of the Si substrate 41 so as to correspond to the device regions defined by the isolation structure 41S. Further, a gate electrode 53 of layers of the polysilicon film 43A and the WSi film 43B of FIG. 6A is formed on the gate oxide film 52.
The STI structure 41S is formed of an isolation groove 41G formed in the Si substrate 41 and a CVD-SiO2 layer 41s filling the isolation groove 41G. A thermal oxide film 41t is formed on the interface between the isolation groove 41G and the CVD-SiO2 layer 41s so as to prevent carriers from moving along the interface.
The CVD-SiO2 layer 41s protrudes slightly from the surface of the Si substrate 41 in the isolation structure 41S. The gate electrode 53 formed of the polysilicon film 43A and the WSi film 43B extends so as to cover the CVD-SiO2 layer 41s. 
A SONOS-type flash memory of this configuration has the merits of simplicity in configuration and storability of multi-level information. However, if the density of integration of the memory integrated circuit is increased, the adjacent drain diffusion layers 41A come close to each other, so that it becomes difficult to avoid the occurrence of a punch-through phenomenon even if the punch-through preventing diffusion layer 41a is provided. Further, if the impurity density of the punch-through preventing diffusion layer 41a is increased so as to control the punch-through phenomenon, the threshold characteristics of the transistors change.
Japanese Laid-Open Patent Application No. 8-186183 proposes a SONOS-type flash memory 60 shown in FIG. 7.
Referring to FIG. 7, n-type diffusion regions 61A serving as a bit-line diffusion layer are formed on the surface of the p-type si substrate 61. Further, grooves 61G are cut into the surface of the Si substrate 61 so as to cross the n-type diffusion regions 61A. An ONO film 62 is formed in the surface of the substrate 61 on which the grooves 61G are formed. Further, a gate electrode 63 is formed on the ONO film 62.
In the flash memory 60 of this structure, the bit-line diffusion regions 61A adjacent to each other across each groove 61G form source and drain regions. A channel is formed along the ONO film 62 between the source and drain regions in the Si substrate 61. Then, information is stored in the form of an electric charge in the proximity of either on of the bit-line diffusion regions 61A in the ONO film 62 by the writing operation described previously with reference to FIG. 3A.
In the flash memory 60, even if the linear distance between the source diffusion region and the drain diffusion region is reduced as a result of miniaturization, the channel extends, bending along the surface of the groove 61G. therefor, the punch-through phenomenon can be effectively controlled.